//md5 03d5722f3ff7b87d071d06154968ad64
(function() {
  var _, _expr, _importLib, all0, all1, bin, cat, chdl_base, dec, expand, has0, has1, hasEven1, hasOdd1, hex, infer, mem_model, oct;

  chdl_base = require('chdl_base');

  ({_expr} = require('chdl_utils'));

  ({cat, expand, all1, all0, has0, has1, hasOdd1, hasEven1} = require('chdl_operator'));

  ({infer, hex, oct, bin, dec} = require('chdl_base'));

  ({_importLib} = require('chdl_transpiler_engine'));

  module.paths.push('/home/lisiyu/work/project/fft/src');

  _ = require('lodash');

  mem_model = class mem_model extends chdl_base.Module {
    constructor(data_width, data_depth, delay) {
      super();
      this.data_width = data_width != null ? data_width : 128;
      this.data_depth = data_depth != null ? data_depth : 128;
      this.addr_width = 32;
      this.delay = delay != null ? delay : 1;
      this._port({
        mem_port: {
          addr: chdl_base.input(this.addr_width),
          wdata: chdl_base.input(this.data_width),
          rdata: chdl_base.output(this.data_width),
          we_n: chdl_base.input(),
          ce_n: chdl_base.input()
        }
      });
      this._mem({
        mem: this._localVec(this.data_width, this.data_depth)
      });
      this._wire({
        rd_data: this._localWire(this.data_width)
      });
      this._reg({
        rd_data_dly: this._localReg(this.data_width),
        port: {
          ce_n: this._localReg(),
          we_n: this._localReg(),
          addr: this._localReg(this.addr_width),
          wdata: this._localReg(this.data_width)
        }
      });
      this._channel();
    }

    build() {
      var addr_t;
      this._assign(this.port.ce_n, '37')(() => {
        return _expr(chdl_base.Expr.start().next(this.mem_port.ce_n), '37');
      });
      this._assign(this.port.we_n, '38')(() => {
        return _expr(chdl_base.Expr.start().next(this.mem_port.we_n), '38');
      });
      this._assign(this.port.addr, '39')(() => {
        return _expr(chdl_base.Expr.start().next(this.mem_port.addr), '39');
      });
      this._assign(this.port.wdata, '40')(() => {
        return _expr(chdl_base.Expr.start().next(this.mem_port.wdata), '40');
      });
      this._always('41', () => {
        return this._if(chdl_base.Expr.start().next("(").next("!").next(this.port.ce_n).next(")").next("&&").next("(").next("!").next(this.port.we_n).next(")"), '42')(() => {
          return this.mem.set(this.port.addr, _expr(chdl_base.Expr.start().next(this.port.wdata), '43'));
        })._endif();
      });
      addr_t = this._localWire(this.addr_width, "addr_t");
      this._assign(addr_t, '45')(() => {
        return _expr(chdl_base.Expr.start().next(this.mem_port.addr), '45');
      });
      this._assign(this.rd_data, '46')(() => {
        return this._if(chdl_base.Expr.start().next("(").next("!").next(this.mem_port.ce_n).next(")").next("&&").next(this.mem_port.we_n), '47')(() => {
          return _expr(chdl_base.Expr.start().next(this.mem.get(addr_t)), '48');
        })._else('49')(() => {
          return _expr(chdl_base.Expr.start().next(hex(this.data_width, 0)), '50');
        })._endif();
      });
      this._assign(this.rd_data_dly, '52')(() => {
        return _expr(chdl_base.Expr.start().next(this.rd_data), '52');
      });
      if (this.delay) {
        return this._assign(this.mem_port.rdata, '55')(() => {
          return _expr(chdl_base.Expr.start().next(this.rd_data_dly), '55');
        });
      } else {
        return this._assign(this.mem_port.rdata, '57')(() => {
          return _expr(chdl_base.Expr.start().next(this.rd_data), '57');
        });
      }
    }

  };

  module.exports = mem_model;

  return module.exports;

}).call(this);
